A disk array apparatus includes a cache memory (a disk cache memory), which is a high-speed device, to reduce data access time. Further, the disk array apparatus includes a nonvolatile memory to save data stored in the cache memory, which is a volatile memory. As the nonvolatile memory, a flash memory (an EEPROM) is used. Consequently, when a main power supply for the disk array apparatus is failed, data stored in the cache memory is saved in the nonvolatile memory.
In a storage device system, it is proposed to provide, in each node, a cache memory, a nonvolatile memory, a copy unit which copies write data stored in each cache memory of the own node and other nodes to the nonvolatile memory, operation-mode switching means for separating the copy means from processing and switching the copy means to a write-through operation when a failure of an inter-copy means interface is detected, write-back means for writing, when an operation mode is switched, the write data stored in the nonvolatile memory in a disk device, and diagnosing means for diagnosing the copy means at a time of a startup after the copy means is replaced.
In a computer system that performs disk cache, there is proposed a control system for the disk cache for selecting a copy-back system or a write-through system of the disk cache control by comparing remaining power of a rechargeable battery detected by remaining-power detecting means and a voltage setting value set by the voltage-value setting means.
In a disk control apparatus, there is proposed means for supplying, when an electric power failure occurs, an electric power failure detection signal from a power supply circuit to a read/write circuit, automatically starting the read/write circuit according the electric power failure detection signal, performing data transfer from a disk cache memory to an EEPROM according to a predetermined parameter value, and saving data of a write cache in the EEPROM.
In a storage system, it is proposed to provide, in addition to a volatile cache memory, a nonvolatile memory that is a memory of a type capable of continuing to store data irrespective of presence or absence of power supply, to set a volatile cache memory as a temporary storage destination of data according to an access command from a host apparatus, and to copy, when power supply from a primary power supply to the volatile cache memory is absent, data stored in the volatile cache memory to the nonvolatile memory by a power supply from a battery.
In a backup apparatus including a nonvolatile memory to which a battery is built-in, it is proposed to provide means for detecting that a power supply voltage reaches an intermediate voltage between a voltage at which write protection is applied to a memory and a normal power supply voltage, and for interrupting to a central processing unit, means for detecting that the power supply voltage reaches an intermediate voltage between a voltage at which interruption is applied by this means and the voltage at which the write protection for the memory is applied, and for applying reset to the central processing unit, and means for setting a most significant bit of an address bus to 0 such that an address allocated to the memory is not selected when the reset is applied by this means.    Patent Document 1: Japanese Laid-Open Patent Publication No. 2006-277205    Patent Document 2: Japanese Laid-Open Patent Publication No. 06-309232    Patent Document 3: Japanese Laid-Open Patent Publication No. 06-309234    Patent Document 4: Japanese Laid-Open Patent Publication No. 2008-108026    Patent Document 5: Japanese Laid-Open Patent Publication No. 05-35614
During the electric power failure of the main power supply for the disk array apparatus, an electric power for data saving is supplied from a battery to a CPU, a cache, a nonvolatile memory, and a controller for the nonvolatile memory. However, the electric power that can be supplied by the battery, in other words, a battery capacity gradually deteriorates depending on outside temperature and the number of times of charging. Therefore, at a time when the electric power failure of the main power supply for the disk array apparatus, term in which the electric power for the data saving can be supplied also gradually decreases and an amount of data that can be saved also gradually decreases.
On the other hand, in a flash memory used as the nonvolatile memory, there is a limit in a number of times of writing. In other words, since a memory cell is destroyed little by little while writing is repeated, a writable area, in other words, a saving area gradually decreases.
Therefore, there is a possibility that, during the electric power failure of the main power supply for the disk array apparatus, entire data stored in the cache memory, in other words, data equivalent to a cache capacity cannot be saved in the nonvolatile memory (a state in which the data cannot be saved occurs). This is due to both or one of the deterioration in the battery life and the decrease in the writable area of the nonvolatile memory. In this case, since the data stored in the cache memory cannot be guaranteed, the disk array apparatus needs to change a write-back state at that time to a write-through state.
FIG. 9 is a saving processing flowchart of the cache memory in the disk array apparatus.
The disk array apparatus determines whether the battery capacity is equal to or larger than the capacity of a cache memory, in other words, the battery capacity is equal to or larger than a battery capacity which can save the data of the cache memory to a flash memory, and determines whether a saving area of the flash memory is equal to or larger than the capacity of the cache memory (step S101). When the battery capacity is equal to or larger than the cache capacity and the saving area of the flash memory is equal to or larger than the cache capacity, the disk array apparatus continues the write-back state (step S102). When the battery capacity is smaller than the cache capacity, or when the saving area of the flash memory is smaller than the cache capacity, the disk array apparatus changes the write-back state to the write-through state (step S103).
In the write-back state, at a point when data from a host computer is stored in the cache memory, the disk array apparatus issues a notification of writing completion to the host computer. However, in the write-through state, the disk array apparatus does not issue the notification of writing completion to the host computer until the data from the host computer is stored in a disk. Therefore, the performance of the disk array apparatus from the viewpoint of the host computer is deteriorated by the change.